The present invention relates to a circuit for generating an address of a random access memory (abbreviated RAM hereinafter), and more particularly to, a circuit for designating write and read addresses of a RAM which functions as a delay circuit in an audio surrounding system.
The recent audio surrounding system which delays digital audio data often uses a RAM as a delay circuit, in which the audio data is written at a write address into the RAM, and it is read at a read address therefrom by a predetermined delay time. The write and read addresses are designated by an address generation circuit.
One type of a conventional address generation circuit comprises a pointer register, a write offset register set, and a read offset register set. The pointer register indicates a pointer value of each write and read addresses. The write and read offset register sets respectively include a plurality of offset registers each having a different offset value. The offset value indicates an offset from the pointer. Therefore, the write and read addresses are designated to provide a predetermined delay time, for instance, by the addition of the pointer value and the offset values.
Another type of a conventional address generation circuit modifies the former one, so that the write and read offset values are obtained from one common offset register set. For this common-use purpose, this address generation circuit further comprises a pointer register controller which changes a pointer value of the pointer register dependent on a state of a write and read control signal.
Still another type of a Conventional address generation circuit includes a RAM which is divided into a plurality of storage regions each having a different delay amount. Each data is stored in a corresponding storage region based on the required delayed amount.
However, the above conventional address generation circuits have the following disadvantages:
1. In the first conventional one, the construction thereof becomes complicated, since this address generation circuit includes two offset register sets each having a plurality of offset registers for different offset values; PA0 2. In the second conventional one, the construction thereof and a control system thereof become complicated due to the inclusion of the pointer register controller; PA0 3. In the third conventional one, it is difficult to effectively utilize all the storage regions, when a required delay time is small as compared to a delay time determined by an address length of a divided storage region.